Practical Evaluation of ESD Protection Devices for High-speed Interface

نویسندگان

  • Kouichi Yoshioka
  • Hideaki Tokunaga
  • Osamu Shibata
  • Takeshi Iseki
چکیده

In this paper, three types of ESD protection devices with low capacitance used for high-speed interfaces are evaluated by transmission line pulse measurement. Different suppression characteristics were observed for rise time and pulse width. The results suggest there could be some differences in practical system-level ESD tests among ESD protection devices. An ESD gun test confirms this, and polymer ESD devices are found suitable to protect high-speed signaling.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Latch-up Considerations for ESD Protection Devices on High Speed Serial Interface Applications

Introduction As process geometries of chipsets that drive today’s high speed serial interfaces become smaller and consequently more sensitive to transients such as ESD, the challenge to provide adequate protection for these chipsets is growing. A type of device that exhibits a negative resistance on a portion of their current−voltage characteristic is one solution to overcome the protection cha...

متن کامل

Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process

Electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interface circuits in a 130-nm CMOS process is presented in this paper. First, the ESD protection diodes with different dimensions were designed and fabricated to evaluate their ESD levels and parasitic effects in gigahertz frequency band. With the knowledge of the dependence of device dimensions on ESD robustness...

متن کامل

Analysis and Design of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF ICs

Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixedsignal and RF circuits. This paper presents quantitative methodologies to analyze the performance degradation of these circuits due to ESD protection. A detailed s-parameter-based analysis of these high-frequency systems illustrates the utility of the distributed ESD protection sche...

متن کامل

Whole-Chip ESD Protection Strategy for CMOS Integrated Circuits in Nanotechnology

Abstract On-chip electrostatic discharge (ESD) protection circuits had been built in IC chips to protect the devices and circuits against ESD damage. But, ESD protection circuits constructed with the scaled-down CMOS devices are very weak to ESD stress. Therefore, novel ESD protection solutions must be developed to overcome this reliability challenge for integrated circuits fabricated in the na...

متن کامل

ESD Protection Design Using Copper Interconnects: More Robustness And Less Parasitics

This report presents a comprehensive investigation on the advantages of using copper interconnects in ESD protection designs. 4KV GGMOS ESD protection structures using Cu interconnects, a 2GHz ring oscillator circuit and a low-power, high-speed Op Amp circuit were designed for comparison study. In Phase I, simulation results show that, while ESD protection devices may inevitably affect circuit ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2009